When a semiconductor device such as a metal-oxide-semiconductor field-effect transistors (MOSFETs) is scaled down through various technology nodes, high k dielectric material and metal are adopted to form a gate stack. However, in a method to form metal gate stacks for n-type MOS (nMOS) transistors and p-type MOS (pMOS) transistors, various issues may arise when integrating the processes and materials for this purpose. For example, when the p-type metal gate of a pMOS transistor is exposed to a polysilicon removal process at a step to form a n-type metal gate, the aluminum and p metal layer filled in the p-type metal gate electrode are damaged, recessed or removed by the etching process to remove the polysilicon from the nMOS transistor region. Furthermore, the n-type metal layer is subsequently deposited in the recessed p-metal gate. This causes high resistance of the p-type metal gate and device performance degradation, such as work function variation of the pMOS metal gate and the threshold voltage shift of the pMOS transistor. Therefore, there is a need for a fabrication method to address the above concerns.